1. Field of the Invention
This invention relates to integrated circuit (IC) fabrication technology, and more particularly, to a method of fabricating a dielectric structure for a storage capacitor in dynamic random-access memory (DRAM).
2. Description of Related Art
With the advent of advanced and state-of-the-art semiconductor fabrication technologies, IC devices are now being downsized to the submicron or even deep submicron levels of integration to provide extremely high packing densities of transistor elements therein. In the case of DRAM, however, the downsizing would also reduce the capacitance of its storage capacitor, resulting in a degraded data retaining capability.
The storage capacitor in each DRAM cell is composed of a pair of oppositely arranged electrodes and a dielectric structure sandwiched therebetween. Fundamentally, the data retaining capability of the DRAM increases with the capacitance of its storage capacitor; and the capacitance of the storage capacitor is proportional to the dielectric constant of the dielectric structure and inversely proportional to the thickness of the dielectric structure. The dielectric structure is typically formed from silicon oxide or silicon nitride. Silicon oxide has a dielectric constant of about 3.8, and silicon nitride has a dielectric constant of about 7. Therefore, silicon nitride is more preferable than silicon oxide as the dielectric material used to form DRAM's storage capacitor.
A silicon nitride based dielectric layer is conventionally formed through a low-pressure chemical-vapor disposition (LPCVD) process, with SiH.sub.2 Cl.sub.2 or SiH.sub.4 serving as the reactant to be reacted with NH.sub.3 for the forming of silicon nitride. One drawback to the use of LPCVD process to form silicon nitride based dielectric layer, however, is that when the thickness is downsized to below 200 .ANG., it would cause the resultant silicon nitride layer to be formed with an undesired rugged surface with many punctures, which would make the resultant storage capacitor to suffer from leakage current, and thus unreliable to use. This structural defect can be eliminated by increasing the thickness of the silicon nitride layer. However, this would make the resultant storage capacitor low in capacitance.
One solution to the foregoing problem is to use an ONO dielectric structure, which is a stacked structure consisting of a first oxide layer (O), a silicon nitride layer (N) over the first oxide layer, and a second oxide layer (O) over the silicon nitride layer. Typically, the first oxide layer is a primitive oxide layer; while the second oxide layer is formed through a wet-oxidation process, by which the wafer is placed in an oven with water serving as the oxidant to undergo a thermal oxidation process at a temperature of 800.degree. C. for a continuous period of about 30 minutes. This process can help mend the above-mentioned structural defect in the resultant silicon nitride layer to prevent the leak-age problem.
One drawback to the foregoing method, however, is that the effective dielectric constant of the overall dielectric structure would be decreased due to the use of two oxide layers and the increased thickness from the wet-oxidation process. The capacitance of the resultant storage capacitor is therefore still unsatisfactorily low.
There exists, therefore, a need for a new semiconductor fabrication method that can allow the dielectric structure between the electrodes of a storage capacitor in DRAM to be as thin as possible while nevertheless allowing the resultant dielectric structure to be substantially free from the above-mentioned structural defect.